[master] e7ea0de7d give timing critical test a bit more margin
Nils Goroll
nils.goroll at uplex.de
Thu Apr 9 13:18:06 UTC 2020
commit e7ea0de7db04aff585d7e6048f2cd37a7c66a1a1
Author: Nils Goroll <nils.goroll at uplex.de>
Date: Thu Apr 9 15:03:47 2020 +0200
give timing critical test a bit more margin
we want to make sure that we do not hit timeout_idle as long as we stay
below it, but the margin of just 100ms has triggered a false negative.
Double the margin to 200ms...
see with vtest (c4u lines extracted)
**** c4u Loop #3
** c4u === delay 0.3
*** c4u delaying 0.3 second(s)
**** dT 2.025
** c4u === sendhex 0d0a
**** c4u sendhex| 0d 0a
---- c4u Write failed: Socket is not connected
diff --git a/bin/varnishtest/tests/b00067.vtc b/bin/varnishtest/tests/b00067.vtc
index 612f5fcd5..9479617a8 100644
--- a/bin/varnishtest/tests/b00067.vtc
+++ b/bin/varnishtest/tests/b00067.vtc
@@ -82,10 +82,10 @@ client c2u -connect "${tmpdir}/v1.sock" {
client c3u -connect "${tmpdir}/v1.sock" {
loop 3 {
# send a periodic CRLF
- delay 0.3
+ delay 0.2
sendhex 0d0a
}
- delay 0.3
+ delay 0.4
expect_close
} -start
@@ -94,10 +94,10 @@ client c4u -connect "${tmpdir}/v1.sock" {
rxresp
loop 3 {
# send a periodic CRLF
- delay 0.3
+ delay 0.2
sendhex 0d0a
}
- delay 0.3
+ delay 0.4
expect_close
} -start
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