Memory barriers

[Nils Goroll]

Hi Poul-Henning and All,

i noticed this:

http://varnish-cache.org/changeset/4796

Once you're at it, it would appear to me that adding differentiated macros for
load/store/both (AMD64: lfence/sfence/mfence) or even more specific macros was a
good idea.

http://markmail.org/message/fzzgebam4bwhfiv3

Solaris has membar_consumer_producer for load/store and membar_enter/exit for
the general case:

http://docs.sun.com/app/docs/doc/816-5168/membar-producer-3c?a=view

While membar_enter and exit are the same on AMD64, they are not on SPARC and
probably other RISC:

http://cvs.opensolaris.org/source/xref/onnv/onnv-gate/usr/src/uts/sparc/v9/ml/lock_prim.s#117
http://developers.sun.com/solaris/articles/atomic_sparc/#MEMBARinstruction

Apologies if this just bores you, it was just that the commit had triggered my
personal interest and I'm simply sharing what appeared relevant to me.

Nils