Memory barriers

[Poul-Henning Kamp]

In message <4BF24C0A.40508 at schokola.de>, Nils Goroll writes:

>http://varnish-cache.org/changeset/4796
>
>Once you're at it, it would appear to me that adding differentiated macros for
>load/store/both (AMD64: lfence/sfence/mfence) or even more specific macros was >a good idea.

Only if I need them.

The membars I need are (until now) only for store order since the data 
structures in question are internally consistent with the right store order.

This stuff is still experimental any way, so I'm not making any
firm decisions yet.

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